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Welcome back, Tim ‘Mithro’ Ansell!
- Tim has been on the show twice before:
- First time was talking about microcontroller and making a device out of that
- Second time was talking about FPGAs
- Third time is looking at creating the ASIC
- Tim says the next level down will be making the actual chips like Sam Zeloof, but he prefers bits to atoms.
- Talk at Chaos with Bunnie about dabbling in the others’ fields, like thinking about the lifetime of software (and applying quality engineering)
- What is an open source PDK? Github repo
- Three main components to building an IC
- The RTL and design (code)
- The tools – compiler / interpreter in SW
- How does the physics work?
- Called the PDK – process design kit
- In machine readable form
- Similar to the stackup of a PCB
- Tim likes the tool SKiDL by past guest Dave Vandenbout.
- Mike Englehardt has been on before talking about SPICE.
- Why were PDKs secret before? Especially since it would be very hard to reverse engineer the PDK
- In the 80s it was open, but it changed over time. Chris posits because of VC investment? Now it’s cultural that the chip industry is not open
- “Open source has won in the sofware world” and the arguments feel the same
- QuickLogic officially supporting their tools with open source tools, as stated in a blog post by CEO Brian Faith
- RISC V ISA (instruction set architecture)
- “The secret power of open source means engineers don’t have to spend time talking to lawyers”
- Open source standardizes legal equations
- The ASIC world has many groups of lawyers
- Only ideas that people are extremely confident about will get explored
- Moore’s law slowing down, compute needs growing
- Taking risks is hard because of all the roadblocks
- RISC V has opened up the ISA space to try exploring ideas that others had written off as bad ideas
- Tim gave a FOSSi “Dial Up” talk, which we will refer to at different timestamps to discuss the slides he reviews.
- Single core has flattened out for 10 years (7 minute mark on the video)
- More cores needs more memory bandwidth
- Power consumption issues
- Tim is in a group the focuses on developer productivity at Google
- That’s why they’re contributing to tools to make things faster
- Security is also dependent upon how fast you can deploy changes
- Making hardware accelerators using TPUs
- Using machine learning to develop TPU
- 130 nm came out in 99 (26 minute mark)
- The PDK and resulting silicon will be used for areas where cost > performance, like IoT.
- Good for microcontroller, but not a high speed
- Beagleboard has PRUs
- They expect some users will make specialized devices, like putting a RISC V per pin or similar.
- What’s the plan for analog?
- First thing released was digital standard cells, but they plan to publish low level transistor models, including parametric models. Unfortunately they are currently blocked on getting that work released.
- What tools are available?
- Similar to FPGA toolchain sides
- First step for FPGA and ASIC is synthesis, like using Yosys (lead by Claire Wolf)
- P&R is different
- More freedom in ASICs
- QFlow ASIC PNR (Tim Edwards)
- FPGA PNR are different toolchains:
- NextPNR (lead by Dave Shah)
- VPR (grandfather of Quartus 2)
- DARPA launched a program called IDEA (Andreas Olofsson), which resulted in another PNR for ASICs: The Open Road project
- Tools for doing an open source flow
- Submitted list by sine_osc
- Magic (older than the BSD license!)
- Xyce is fast
- LTSpice used by LT designers
- Schematic capture is still not easy (maybe KiCad?)
- Google will be doing a free shuttle run for open source chips
- Will be sending it to eFabless, they will bundle the shuttle
- 40 designs total (unless they get a large response)
- Wafer chip scale package (CSP) 4x4mm
- 50 i/o, 40 will be for design
- Might send back chips on castellated PCB
- To get your design approved, it must be using the right license.
- They will release a full list of licenses that will work, but Apache2 is guaranteed.
- Also needs to pass DRC, which will be published in the repo soon.
- Skywater PDK slack channel
- Lottery system if they get more than 40 designs
- Will be starting first run in Mid-November, Will be doing more runs after that.
- Out of 16 mm^2, only 10 mm^2 is available. The rest will be for “the harness”, a RISC V processor that can connect ‘virtual GPIO’ to turn things on or off.
- As a reference for size, could probably fit 10 RISC V cores on the 10 mm^2
- In contrast to MOSIS or Europractice, they want to fab out 100 – 400 of the chips so that they can share.
- Slack channel skywater-pdk
- J-Core, an SH based processor
- Power PC is now an open ISA
- Tim has published an Inspiration document.
- If you’re interested, you should join the mailing lists, especially the announce one.
- The slack invite link is on the announce list. They will try to set up an invite bot for later.
- Check out the FOSSi dial up talk series for future information about development.
- Mohammed from eFabless will be giving a talk about Open Road and will be showcasing demo chips, which are currently out for manufacturing. These might act as good templates.
- Need tutorials on all of the software (KLayout, MAGIC)
- Project from University of Michigan, FASoC, treats analog design like digital design.
- “Screaming inside their heart”
- Craig Bishop episode
- Adrian Tang episode
- The physics act more ideally in the small space of silicon
- Hoping to have a similar OSHpark for silicon
- “Chips4makers” is one that is trying to make “the OSH Park for ASICs”, but they are more focused on retrocomputing.
- Trying to seed and build an ecosystem
- “The things that will be most successful in this space will be those that build on each other and work together”
- Traditional ASIC designers should be prepared to do thing differntly
- Can open source be profitable? IBM bought Red Hat for $30B
- The next wave of software is “software AND”, the hardware is just a means to an end
- Contact Tim directly: email@example.com
- Better to go on the slack and ask there
This was a long and interesting episode.
I would love to hear more of that stuff, at the end, maybe around 1:50h into the podcast a really important thing was mentioned by Chris:
If you share all your knowledge, who is going to be paid, I think the payment issue is the thing that is holding a lot of intelligent people back from sharing a lot of knowledge, generally today I have the feeling people share a lot if it is their business, but all the people in good engineering positions, they just keep low profile earn a lot of money.
Maybe we need to talk about a new system of incentives, I for myself would not openly share all my knowledge on the interwebs, personally hell yeah i would explain every little detail 🙂
Thanks a lot, keep on going.
Chris Gammell says
The upcoming show is with eFabless co-founder Mohammed Kassem, we will touch on some of these issues! Should be out on Sunday
Shaun Meehan says
This was a great episode! I’ve been following this project for a while now but it was interesting to hear all the details. I can’t wait to check out the ‘Open ADC’ design someone comes up with.