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Welcome Brian Faith, CEO of QuickLogic!
- Past guest Tim Ansell introduced us to Brian, from their work together on the open toolchain.
 - They met at a tradeshow and Brian declined the first time, only to be convinced later.
 - QuickLogic IP licensing
 - Brian attended OR Conf in Bordeaux, where they were watching talks and excited by future growth of users of the open toolchain.
 - Resisted for a year
 - Brian started at QuickLogic during the “schematic era” (when FPGAs were designed using graphical schematic of logic blocks)
 - Previously their toolchain
- Worked with early versions of Synplicity, but later switched to using Mentor Graphics Precision
 - There was no bundled simulator
 - Proprietary Place and Route (P&R)
 
 - The new QuickLogic approach is Symbiflow
 - It’s also about the software engineer
 - A community member ported NuttX to the platform
 - What did QuickLogic give up, in order to use the Symbiflow toolchain? They had to publish the spec of the bitstream
 - What could you do with the spec of the bitstream? Why is it secret? Apparently, due to history and a generally closed off ecosystem in FPGAs.
 - QuickLogic is targetign selling to software engineers, not just FPGA engineers. This has become much easier with python targeting FPGAs (LiteX, Migen)
 - Software users will help enable more “mass customization”
 - Making software designs into silicon
 - Open Hardware Group
 - RISC V
 - Global Foundries at Munich
 - The Artic Pro 2 will be built on the Global Foundries 22FDX, which is their 22 nm process
 - Hardware/Software partitioning
 - They’re building a test chip
 - QuickFeather
 - SensiML is the web-based machine learning toolset. The team came from the Intel Curie group.
 - SensiML was bought by QuickLogic at the beginning of 2019, but they still offer services for chips outside the QuickLogic portfolio as well.
 - Chris doesn’t think a threshold detect algorithm would be up to the task in many cases.
 - QuickLogic and SensiML are sponsoring a Hackster contest targeted at projects that will help prevent climate change.
 - You send in your sensor data, SensiML gives back models you include as a “black box” algorithm
 - The web interfice allows you to dial in performance algorithms. You can also update the data/model later if you want to tweak based on new data or different parameters.
 - There is an example data set on github using a PM2.5 sensor
 - QuickLogic Open Reconfigurable Computing (QORC)
 - Size of the model depends on perfomance dialed in on the website
 - The models are set to run on on Cortex-M4, specifically the EOS S3
 - TensorFlow lite for microcontrollers
 - APIs for convolution
 - eFPGA = embedded FPGA
 - In the case of the EOS S3, it’s roughly equivalent to 1000-2000 LUTS
 - USB in the FPGA without a dedicated (hard) USB core can do USB 1.1 full speed data speeds.
 - Videos and instructions
 - Building a proof of concept
 - Community edition of SensiML gives you enough access for entering the contest, trying out models at home (non-commercial).
 - If you are developing a commercial product, SensiML has commercial subscription prices (Chris thinks they’re reasonable, relative to hiring an FPGA/DSP engineer)
 - Removing the gyro using SensiML
 - Wrist worn wearables for applications like remote control
 - Industrial applications
 - Consumer is still a focus
 - Gerry Roston talking about data and monitoring for large scale auto manufacturing facilities
 - They are targeting many of their classic customers in the Automotive / MIL / Aero industry, as well as new ones. They are avoiding the server / datacenter industry.
 - QuickLogic licenses things like their IP blocks, memory blocks, math blocks for people to design into future silicon.
 - If you licence IP from QuickLogic (fabric), you will also be able to use Symbiflow for your silicon product.
 - Interested in learning more and giving it a try? Check out the Hackster contest
 - EOS S3 page
 - Great video tutorials
 


Unclear about the “e”FPGA… what is the difference between the EOS S3’s “MCU + eFPGA” and a traditional FPGA with hard-IP ARM (ex. Microsemi SmartFusion2, Xilinx Zynq, etc)?
For example, I assume the EOS S3 is NOT instant-on.. but rather SRAM based and must be configured at power-on?
The Quicklogic website doesn’t simply show what the difference between the various Quicklogic antifuse FPGAs… Eclipse,EclipseII,EclipsePlus,QuickRAM,PolarPro,PolarProII, pASIC3..
Finally, is there a list of soft-IPs that are available either for free, or for purchase (ex. 1553)?