Dr. Howard Johnson, master of the black magic of high speed digital signals, will be our guest on next week’s show! We have a few questions cooked up for him, but want to know what our audience members want to know about! Try and stump him with your questions or pose a problem you’ve experienced with crosstalk, high speed propagation, losses or any other kind of issue you think he might be able to help you with! Leave your questions in the comments and tune in next week to hear him answer them on the show.
What is your favorite site/tutorial/forum for understanding what everyone must know about high speed designs?
In CPU/waffer world, we constantly hear that the “physical boundary will be hit very soon and then you hear from a new, clever way of going beyond it (new processes, 3D transistors, etc..) Is it the same in high-speed communication, or will we really hit a brick wall sooner than later (to be clear, I don’t ask to predict the future, I would want to have your opinion on “is there room for improvement and are there new ideas” or “just crank it to eleven”).
Right, or in a more Feynmanian way of asking it, “Is there really plenty of room at the bottom?”
Unfortunately, I’m not familiar with Dr. Johnson’s books so maybe this is answered already but I’ll ask anyways:
As digital signals reach ever higher speeds a lot more analog problems rear their ugly heads like transmission lines, pulse shaping, channel cancellation, etc. Are these problems typically dealt with by an analog guy, a digital guy, or more collaborative methods? Also, have chip vendors come up with off the shelf methods for some of these problems or is there still a lot of discrete design going on?
Q: Does the high-speed electronics industry have to deal with problems caused by cosmic rays interfering with the operation of sensitive circuits and if so how can it be proved that cosmic rays are to blame?
Now if you’ll excuse me I need to go find my tinfoil hat. 🙂
I’m very interested about PCB routing rules for high-speed stuff. Please ask him about it!
Ah, so this is the show page. I apologize for the extra posts.
My question for Dr. Howard is:
How does he think the handbook has held up over time? Assuming he had the time, are there any chapters in particular he would update?
I second this question. I was thinking of asking something like “What are the most important new (post-book) things a high-speed digital designer should know?”
One other question and follow-up:
Now that so many of the newer ICs have adaptive preemphasis and equalization on their lanes, and receivers that can function with practically no eye, is it still important for the typical PCB engineer to understand high speed digital design? Would his answer change if there were no connectors in the transmission line?
I personally love understanding the intricacies of high speed digital design, but I am constantly amazed at the things I can get away with to meet difficult mechanical constraints when using newer links. Sometimes it seems like I would have to make an effort to break them.
I’m really surprised to hear this. My experience has been the opposite. For example, on a 5gpbs link every little detail is important. The dielectric material, stub length of a via, shape of the capacitor pad, even the shape of the anti-pad on a via. We run a lot of simulations to make sure that the channel is properly designed. Else, we have no hope of getting it working. However for a 1Gbps link, none of these are critical.
Also, the newer chips have much tighter requirements. I have seen chips require <10mVpp of noise, and very tight jitter requirements on input clocks. It's getting to the point where SI is the most important aspect of the design. Mechanical and even sometimes software have to work around the SI needs for a board.
This is an important thing that I left out. For my boards nothing operates at faster than 3Gbps, the vast majority of nets run 1Gbps and under. But this does lead to a better rephrasing of the question for Dr Howard, we know the rule for finding the length at which a wire becomes a transmission line, but given newer IC driver and receivers and PCB technologies it seems the threshold where links become “high speed” moves over time. Where would Dr. Howard put this threshold now? Is creating this care/don’t-care threshold a dangerous thing to do?
Actually, now that I really think about this perhaps the high speed serial links never break, due to SI, because they get so much attention. However, at my company anyway, the lowly busses like I2C are always breaking due to SI related issues because no one pays any attention to them. They get routed in the worst possible topologies with so many stubs, drop points and ground breaks. And it often seems like the engineers who do the receivers in those parts don’t think too hard about the problem either. It would be fun to hear any comments or anecdotes along these lines.
Since Dr. Johnson was elected by the IEEE as chief technical editor of Ethernet standards. I would like to know how many more gigabits/sec or years of life is left in the cat 5/6 cabling with RJ45 setup?.
Can Ethernet work effectively as a backplane interconnect in real-time systems?
Here are some possible questions:
1. We know we’re supposed to tied together the analog and digital ground pins on an ADC. They should not go to separate planes connected at some point distant from the ADC. Should they be tied together on the top layer and then grounded with the same via(s)? Or is it acceptable/preferable for them to be connected to the ground plane by separate vias?
2. We know adding series termination at the source of a high-speed digital signal can reduce EMI and improve signal integrity. Is the primary mechanism slowing down the edge rate or impedance matching the source to the trace?
3. Does one of his books have the formula for the impedance of a trace with ground plane beneath and ground on both sides, i.e. coplanar wave guide?
Thought of another question. What are the pros and cons designing with fiber optic lines versus conventional wiring?
Point-of-load regulation with a higher supply voltage rail is becoming more and more necessary with lower voltage supplies (and avoiding resistive losses). What challenges and/or techniques do you suggest in relation to this?
Are there any very low cost (free, preferably) simulation tools you can suggest for modeling the effects of layout on signal integrity?
How many boards should be tested before the designer can be in reasonably confident that the design will work? The first batch might work but it may not have the worst case PCB and ICs. If the boards pass when they are tested at the four corners (high, low voltage and temp), can you assume that there is enough margin in the design to handle the worst case?
I’m pretty sure the answer is “it depends”. But is there a rule of thumb (for every X serial link, build Y boards) or testing methodology that Dr. Johnson recommends?
Thanks.
As a ex tv tech, and signal expert, what does he think of the claims made by monster cables.
Mike.
hey, I’m new to electronics (i’m from suriname) I need a mini circuit for a 9.0V dc input with a 5.oV – 16Khz output.to use as a driver on an (neg – )thyristor current supply. think you guys could help me on this experiment. thank you.