Podcast: Play in new window | Download
Subscribe: Apple Podcasts | RSS
Welcome, Anthony Wall!
- Anthony is a PhD student in the MCCI group at Tyndall, which is a research institution in Ireland.
- Why did companies like Intel and ADI choose Ireland?
- There was a recent history on 99% Invisible about Duty Free, the Shannon Airport and the first Special Economic Zones (which later inspired Shenzhen!). Definitely worth a listen!
- In the 1930s, the flights from NYC to London needed refueling, so they set up the Shannon airport.
- A man named Brenden O’Regan started doing some of the food there (and later invented the Irish Coffee — though the wiki page is contentious on the first one).
- They implemented the first Duty free shop in an airport and later expanded the idea of a tax free zone to a fenced perimeter.
- As for chips, the limestone and lack of seismic activity means litho machines are very stable.
- There is chip industry in Shannon/Limerick, Cork, and Dublin (with different companies, focus areas)
- Like many other industries, there are hiring problems
- The ADC research world isn’t that large.
- Current ADCs allow a different design methodology and can allow for removing a transimpedance amplifier in front of an ADC circuit.
- But putting it all on one chip is difficult
- 1.2V core voltage rail on 65nm, so there are many power considerations
- Why measure current? Parasitic capacitance of each transistor is getting lower, so it gets easier to estimate “filling up buckets” with current.
- Ring oscillator
- Relaxation oscillator – sometimes these are shown as 3 inverters connected in series
- Want it to look like a sawtooth waveform. Dual slope ADCs also use sawtooth waveforms to capture information.
- What tools are available for tweaking the output on a chip design?
- Knows it’s roughly 70 ps to dump charge
- Currently they are mid precision (8 bits-ish) at MHz capture rates
- The chips were designed using the Cadence toolchain
- MPW is run by Europractice, which is similar to MOSIS
- The chip is 4×4 mm and certain high density runs get more. Anthony got about 100 chips back and it cost them 3.5K as an academic institutin
- The MPW was sent to TSMC
- There are different board level packaging options from Europractice
- Building test boards as a chip designer is a different experience. IC software is more constrained than PCB CAD software, even made by the same company like Cadence.
- P Cell – Parameterized cell
- The PDK from the fab is for the digital designers, but analog designers use it too.
- In the chip EDA space: there is Cadence and Synopsis
- Anthony added a graphic of a pair of “Shorts” to the metal layer
- LVS – Layout vs schematic is the method of checking between the two elements of chip design.
- Transistors are a 4 terminal device, you need to think about the body of the chip and how current will flow in the substrate. Chris and Anthony discuss whether this should be the first thing learned in the mental model of a transistor.
- Building higher level components on a design using re-usable blocks.
- Anthony needed to design the digital section of the chip as well, which written in verilog
- He had to downsample the data output on chip and deserialize it.
- Verilog gets synthesized to gate level (using the PDK) and then there is an interface between analog and digital sections
- You can separate different parts of the design by implementing “deep N-well“
- Advice from supervisor – “A PhD is like a religion, it means nothing to anyone else apart from you…you [need to] do it because you believe in it”
- During his PhD, Anthony has been teaching non linear circuits. A small pandemic silver lining is the change in teaching forma: notes handouts, lectures recorded by default (which can be paused), flipped classroom where they can go over home work in Falstad
- Get in touch with Anthony!
Chip Layout:
The 5 small sections down the middle are the ROSCs, the big block in the middle is the synthesised digital (mostly very expensive decoupling cap, with some digital that you can see as a messy glob in the mid-right), the bottom is a 100 ohm termination resistor & the clock buffer.
Die Shot:
On the die micrograph, you can see the density fill pattern we discussed (small squares). These are on the ~order of the wavelength of light, so they cause the diffraction pattern seen also. The bigger wires you can see are the power distribution network. You can also see the split between analog (left) and digital (right) on the IO ring to separate the power domains. If you REALLY zoom in, you can see different colour shading in the green regions (look in the ROSCS and CLK buffer); These are transistors.
